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general description the hi-5000 i s a 1 mbps controller area network (can) transceiver. it interfaces between a can protocol con- troller and the physical wires of the bus in a can network. the hi-5000 supports two modes of operation: normal mode and standby mode. the standby mode is a very low-current mode which continues to monitor bus activity and allows an external controller to manage wake-up. in addition, the hi-5000 provides a split pin to give an output reference voltage of vdd/2 which can be used for stabilizing the re- cessive bus level when the split termination technique is used to terminate the bus. a txd dominant time-out feature also protects the bus from being driven into a permanent dominant state (so- called babbling idiot) if pin txd becomes permanently low due to application failure. the device also has short circuit protection to +/-58v on canh, canl and split pins and esd protection to +/- 6kv on all pins. the hi-5001 is identical to the hi-5000 except the split pin is substituted with a vio supply voltage pin. this al- lows the hi-5001 to interface directly with controllers with 2.5v or 3.3v supply voltages. the hi-5002 provides both the split and differential output amplitude and current drive capability are specifically enhanced to meet the needs of long cable runs typical in many applications such as industrial auto- mation. superior common-mode receiver performance makes the device especially suitable for applications where ground reference voltages may vary from point to point over long distances along the can bus. vio supply voltage pins in a compact 16-pin qfn. all three devices are available in industrial -40 c to +85 c temperature ranges. rohs compliant lead-free options are also available. oo features compatible with iso 11898-5 standard. signaling rates up to 1mbit/s. internal vdd/2 voltage source available to stabilize the recessive bus level if split termination is used (hi-5000 split pin). vio input on hi-5001 allows for direct interfacing with 2.5v or 3.3v controllers. detection of permanent dominant on txd pin (babbling idiot protection). high impedance allows connection of up to 120 nodes. canh, canl and split pins short-circuit proof to +/-58v. will not disturb the bus if unpowered. pin configurations (top views) september 2011 ( 5000 rev. b) 09/11 ds hi-5000, hi-5001, hi-5002 1mbps can transceiver with low power standby mode 8 - pin plastic narrow body soic rxd-4 gnd-2 txd-1 vdd-3 5 - split 7 - canh 8 - stb 6 - canl hi-5000psi rxd-4 gnd-2 txd-1 vdd-3 5 - vio 7 - canh 8 - stb 6 - canl hi-5001psi 16 - pin plasti c 4 x 4mm qfn hi-5002pci gnd 1 gnd 2 vdd 3 vdd 4 12 canh 11 canh 10 canl 9 canl 16 - 15 txd 14 - 13 stdby vio 5 rxd 6 -7 split 8 holt integrated circuits www.holtic.com
hi-5000, hi-5001, hi-5002 block diagram signal function description txd input 100kohm internal pull-up. transmit data input. gnd power chip 0v supply vdd power positive supply, 5v +/-5%. bypass with 0.1uf ceramic capacitor. rxd output receive data output. canl bus i/o can bus line low. canh bus i/o can bus line high. stb input standby mode selection input. drive stb low or connect to gnd for normal operation. drive stb high to select low-current standby mode. split input supplies a vdd/2 output to provide recessive bus level stabilization when a split termination (hi-5000) is used to terminate the bus. 100kohm internal pull-up. vio input connect to a 2.5v or 3.3v supply to allow compatibility of all digital i/o (rxd, txd, stb) (hi-5001) with a low voltage controller input. pin descriptions figure 1. hi-5000 functional block diagram v split driver txd dominant detect txd stb rxd gnd vdd split (hi-5000) canh canl standby control low power standby rx mux main receiver vio (hi-5001) holt integrated circuits 2
functional description operating modes the hi-5000 provides two modes of operation which are selectable via the stb pin. table 1 summarizes the modes. due to an unpowered node with high leakage from the bus lines to ground), the split circuit will force the recessive voltage to vdd/2. short-circuit protection is provided on the canh, canl and split pins. these the short circuit current is limited to less than 200ma typical. a timer circuit prevents the bus lines being driven into a permanent dominant state, which would result in a situation blocking all bus traffic. this could happen in the case of the txd pin becoming permanently low due to a hardware or application failure. the timer is triggered by a negative edge on the txd pin (start of dominant state). if the txd pin is not set high (recessive state) after a typical time of 2ms, the transmitter outputs will be disabled, putting the bus lines into the recessive state. the timer is reset by a positive edge on the txd pin. note that the minimum txd dominant time-out time, tdom = 300s, defines the minimum possible bit rate of 40kbit/s (the can protocol specifies a maximum of 11 successive dominant bits 5 successive dominant bits immediately followed by an error frame). pin txd has a pull up in order to set a recessive level if pin txd is left open. pins txd and stb will become floating if power is lost. this will prevent reverse currents via these pins. internal protection features short-circuit protection txd permanent dominant time-out fail-safe features pins are protected from esd to over 6kv (hbm) and from shorts between -58v and +58v continuous, as specified in iso 11898-5. ? normal mode normal mode is selected by setting the stb pin to a low logic level (gnd). in this mode, the transceiver transmits and receives data in the usual way from the canh and canl bus lines. the differential receiver converts the analog bus data to digital data which is output on the rxd pin (note: the rxd output on hi-5001 is compatible with 3.3v controllers if the vio pin is connected to a 2.5v or 3.3v supply). 2.5v or standby mode is selected by setting the stb pin to a high logic level. in this mode, the transmitter is switched off and a low power differential receiver monitors the bus lines for activity. a dominant signal of more than 3 s will be reflected on the rxd pin as a logic low, where it may be detected by the host as a wake-up request. the device will not leave standby mode until the host forces the stb pin to a logic low. the split pin provides a stable vdd/2 dc voltage. this pin can be used to stabilize the recessive common mode voltage by connecting the split pin to the center tap of the split termination (see figure 7). in the case of a recessive bus voltage dropping below the ideal value of vdd/2 (e.g. standby mode split circuit mode stb pin normal low standby high holt integrated circuits 3 table 1 - operating modes hi-5000, hi-5001, hi-5002
timing diagrams v vv diff(bus) = - canh canl dominant 0.9v 0.5v rxd high low 50% 50% canh canl recessive txd high low t dr(txd) t df(txd) t df(rxd) t dr(rxd) t prop1 t prop2 timing delays txd dominant time-out feature canh canl txd high low recessive dominant transmitter enabled t dom(txd) transmitter disabled hi-5000, hi-5001, hi-5002 holt integrated circuits 4 t rdom
dc electrical characteristics v = 5v 5%, operating temperature range (unless otherwise noted). positive currents flow into the ic. dd limits parameter conditions unit symbol v supply current i recessive: v = v 6 10 ma min typ max supply current dd dd txd dd dominant: v = 0 v 50 70 ma standby mode: txd driver v=v 15 30 a vio supply current i 100 a high-level input voltage (see note 1) v 70%v v + 0.5 v low-level input voltage v 0.5 30%v v high-level input current i v = v or vio 5 0 + 5 a low-level input current i v = 0 v 50 150 a high-level output voltage (rxd pin) (see note 1) v i = 1ma 90%v v low-level output voltage (rxd pin) v i = 1ma 0 0.1 10%v v output voltage (split pin) v 100 a < i < 100 a 0.45v 0.5v 0.55v v standby leakage current (split pin) i -5 +5 a canh dominant output voltage v v = 0 v 3 3.6 4.25 v canl dominant output voltage v v = 0 v (see fig. 2) 0.5 1.4 1.75 v recessive output voltage v , v v = v , r = 0 (see fig. 2) 0.5v 3 v bus output voltage in standby v v = v , r = 0 (see fig. 2) -0.1 0.1 v dominant differential output voltage v v = 0 v, 45 < r < 65 1.5 1.8 3 v recessive differential output voltage v v = v , no load (see fig. 2) 50 0 50 mv matching of dominant output voltage, v v v v (see fig. 4) 100 -40 150 mv steady state common mode output voltage v v = 0v, r = 60 (see fig. 5) 0.5v 3 v txd dd io ih dd dd il dd ih txd dd il txd oh oh dd ol ol dd split split dd dd dd stb o(canh) txd o(canl) txd canh(r) canl(r) txd dd l dd stb txd dd l diff(d)(o) txd l diff(r)(o) txd dd dd o(canh) o(canl) om oc(ss) stb l dd digital inputs (pins txd, stb) digital outputs ? ? ?? ? 2 ? ? ?? ? 2 notes: 1. human body model (hbm). stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. expos ure to absolute maximum rating conditions for extended periods may affect device reliability. 2. junction temperature t is defined as t = t + p . j j amb r , where t is the ambient or operating temperature, p is the power dissipation and r is a fixed thermal resistance value which depends on the package and circuit board mounting conditions th amb th absolute maximum ratings maximum junction temperature storage temperature range: -65c to +150c soldering temperature: (ceramic)......................60 sec. at +300c (plastic - leads).............10 sec. at +280c (plastic - body) .....................+260c max. operating temperature range: (industrial).........................-40c to +85c ......................................................175c 2 supply voltage, vdd, vio : .....................................................................7v current at input pins dc voltages at txd, rxd and stb ..............................-0.5v to v +0.5v : ............................... ......................................................-100ma to +100ma dc voltages at canh, canl and split -58v to +58v internal power dissipation: ..............................................................900mw electrostatic discharge (esd) , all pins ..........................................+/- 6kv dd 1 (voltages referenced to gnd = 0v) hi-5000, hi-5001, hi-5002 holt integrated circuits 5 note: 1. when vio is connected (hi-5001 or hi-5002), limits are referenced wrt vio rather than v . dd
dc electrical characteristics (cont.) v = 5v 5%, operating temperature range. positive currents flow into the ic. dd limits parameter conditions unit symbol min typ max input leakage current, unpowered node i , i v = 0 v 200 + 200 a canh canl dd short-circuit steady-state output current i v = +58v, v open -20 20 ma v = -58v, v openv -200 100 ma v = +58v, v open 100 200 ma v = -58v, v open (see fig. 6) -20 20 ma differential receiver threshold voltage v 1 2v holt integrated circuits 7 application and test information figure 3. can bus driver (dominant) test circuit figure 4. driver output symmetry test. figure 2. can bus driver circuit recessive dominant ~2.5v ~3.5v : v o(canh) ~1.5v: v o(canl) hi-5000, hi-5001, hi-5002 v o(canh) v o(canl) transceiver r l v diff(d)(o) txd stb canh 300 +/- 1% 300 +/- 1% canl + _ v diff(d)(o) 0v r l -12v <= v <= +12v test transceiver txd stb v o(canh) v o(canl) transceiver r l v diff(d)(o) vv-v + om dd o(canh) =v o(canl) v 1 stb txd
holt integrated circuits 8 application and test information figure 6. can bus driver short-circuit test. (note: v1 is a pulse from 0v to v with duty cycle of 99% such that permanent dominant time-out is avoided). dd hi-5000, hi-5001, hi-5002 figure 5. common mode output voltage test. v o(canh) v o(canl) transceiver r l v diff(d)(o) txd stb v 1 v=v oc(ss) o(canh) +v o(canl) 2 -58v or +58v canh canl + _ transceiver txd v 1
holt integrated circuits 9 application and test information figure 7. typical application connections controller txd rxd v dd 5v regulator v bat gnd txd rxd 1 4 8 3 2 7 5 6 v dd gnd stb canl canh split r/2 l r/2 l (optional) can bus hi-5000 controller txd rxd v dd 3.3v regulator v bat gnd txd rxd 1 4 8 3 2 7 5 6 v io gnd stb canl canh r l can bus hi-5001 v dd hi-5000, hi-5001, hi-5002 5v
holt integrated circuits 10 ordering information hi - 500x xxx x lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank hi-5000, hi-5001, hi-5002 description part number vio pin option 5001 split pin option 5000 both split and vio pins available 5002 package description 16 pin plasti c4x4mmqfn (16pcs) (hi-5002 only) part number pci 8 pin plastic narrow body soic (8hn) (hi-5000 or hi-5001 only) 8 pin cerdip (8d) not available pb-free (hi-5000 or hi-5001 only) psi cri
revision history hi-5000, hi-5001, hi-5002 holt integrated circuits 11 p/n rev date description of change 000 new 04/01/11 initial release a 04/29/11 corrected heat-sink note on qfn package drawing. b 09/16/11 update pad and heat-sink dimensions for 16-lead qfn package (16pcs) ds5
package dimensions 8-pin plastic small outline (soic) - nb (narrow body) inches (millimeters) package type: 8hn bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) see detail a 0 to 8 detail a p in 1 .236 .008 (5.99 .21) .154 .004 (3.90 .09) .194 .004 (4.92 .09) .0085 .0015 (.216 .038) .050 (1.27) .033 .017 (.838 .432) .055 .005 (1.397 .127) .0069 .003 (.1753 .074) .0165 .003 (.419 .089) bsc 16-pin plastic chip-scale package millimeters package type: 16pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 4.00 bsc 4.00 bsc 2.80 .10 2.80 .10 0.40 .05 1.00 max 0.20 typ 0.65 bsc 0.30 .05 top view bottom view electrically isolated metal heat sink on bottom of package connect to any ground or power plane for optimum thermal dissipation holt integrated circuits 12
package dimensions 8-pin cerdip inches (millimeters) package type: 8d bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .380 .004 (9.652 .102) .005 min (.127 min) .314 .003 (7.976 .076) .200 max (5.080 max) .248 .003 (6.299 .076) .039 .006 (.991 .154) .163 .037 (4.140 .940) .018 .006 (.457 .152) .056 .006 (1.422 .152) .015 min (.381min) .350 .030 (8.890 .762) .010 .006 (.254 .152) base plane seating plane .100 bsc (2.54) holt integrated circuits 13

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